In order to protect integrated circuit devices (ICs) against damage due to electrostatic discharge, it is common to include either separate ESD protection devices for channeling high ESD currents to ground, or to create self protecting I/O cells in which the same device is used as a high current output driver as well as for ESD protection.
The most compatible ESD protection structure for integration in different BiCMOS/BCD products is a NPN BJT, such as the one illustrated in FIG. 1. The NPN BJT 100 includes a p-type base 102 formed in a n-epitaxial layer 104. The base 102 is contacted through a contact 106. An n-type emitter 108, in turn, is contacted by an emitter contact 110. The BJT further includes a collector comprising a n-sinker region 112, which is contacted by a contact 114 (in this case, through a n+ region 116). The collector is isolated from the emitter 110 by an isolation region 120. The I-V curve of a NPN BJT such as the one illustrated in FIG. 1, displays a distinct S-shaped characteristic as shown in FIG. 2. This is due to avalanche injection conductivity modulation, which takes place at triggering and allows the device to deliver high current densities after triggering (VTR). Although the same avalanche injection conductivity modulation takes place in NMOS and DMOS devices, NMOS and DMOS devices display sensitivity to electrical, thermal and hot carrier overstress, due to the presence of a gate region.
Nevertheless, the NPN BJT also has its limitations, especially when designing high voltage (50–200V) circuits. The combination of high avalanche current and high electric field in conjunction with current redistribution effects at negative differential conductivity (upper part of S-shaped curve of FIG. 2) results in excessive currents and heating in the structure.